[mpich-devel] fastest shared-memory back-end?

[Jeff Hammond]

MPICH configure just asked me to choose ch4:ofi vs ch4:ucx vs ch3.  Does
anyone have an informed opinion on which one is the faster for
shared-memory execution?

My specific use case is NWChem on very large multi-socket Xeon nodes, where
passive target RMA is the primary communication method, hence my primary
concern is asynchronous progress and lack of serialization in RMA.  In the
past, I have observed significant performance issues due to serialization
of RMA accumulate operations acting on non-overlapping memory regions.

Jeff

-- 
Jeff Hammond
jeff.science at gmail.com
http://jeffhammond.github.io/
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